SC418
25
Applications Information (continued)
R1
R2
FB
pin
C
C
C
OUT
L
Low-
side
High-
side
C
L
R
L
Figure 15 Virtual ESR Ramp Current
This network creates a ramp voltage across C
L
, analogous
to the ramp voltage generated across the ESR of a stan-
dard capacitor. This ramp is then capacitively coupled into
the FB pin via capacitor C
C
.
Dropout Performance
The output voltage adjust range for continuous-conduc-
tion operation is limited by the fixed 250ns (typical)
minimum off-time of the one-shot. When working with
low input voltages, the duty-factor limit must be calcu-
lated using worst-case values for on and off times.
The duty-factor limitation is shown by the following
equation.
)
MAX
(
OFF
)
MIN
(
ON
)
MIN
(
ON
T
T
T
DUTY
The inductor resistance and MOSFET on-state voltage
drops must be included when performing worst-case
dropout duty-factor calculations.
System DC Accuracy (V
OUT
Controller)
Three factors affect V
OUT
accuracy: the trip point of the FB
error comparator, the ripple voltage variation with line
and load, and the external resistor tolerance. The error
comparator offset is trimmed so that under static condi-
tions it trips when the feedback pin is 500mV, + %.
The on-time pulse from the SC48 in the design example
is calculated to give a pseudo-fixed frequency of 250kHz.
Some frequency variation with line and load is expected.
This variation changes the output ripple voltage. Because
adaptive on-time converters regulate to the valley of the
output ripple, ?of the output ripple appears as a DC regu-
lation error. For example, if the output ripple is 50mV with
V
IN
= 6 volts, then the measured DC output will be 25mV
above the comparator trip point. If the ripple increases to
80mV with V
IN
= 25V, then the measured DC output will be
40mV above the comparator trip. The best way to mini-
mize this effect is to minimize the output ripple.
To compensate for valley regulation, it may be desirable to
use passive droop. Take the feedback directly from the
output side of the inductor and place a small amount of
trace resistance between the inductor and output capaci-
tor. This trace resistance should be optimized so that at
full load the output droops to near the lower regulation
limit. Passive droop minimizes the required output capaci-
tance because the voltage excursions due to load steps
are reduced as seen at the load.
The use of % feedback resistors contributes up to %
error. If tighter DC accuracy is required, 0.% resistors
should be used.
The output inductor value may change with current. This
will change the output ripple and therefore will have a
minor effect on the DC output voltage. The output ESR
also affects the output ripple and thus has a minor effect
on the DC output voltage.
Switching Frequency Variations
The switching frequency will vary depending on line and
load conditions. The line variations are a result of fixed
propagation delays in the on-time one-shot, as well as
unavoidable delays in the external MOSFET switching. As
V
IN
increases, these factors make the actual DH on-time
slightly longer than the ideal on-time. The net effect is
that frequency tends to falls slightly with increasing input
voltage.
The switching frequency also varies with load current as a
result of the power losses in the MOSFETs and the induc-
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